This invention is directed to DRAMs but can find application in static RAMs and other semiconductor memories as well, and other integrated circuits which have an array of memory cells disposed along orthogonal directions in a reticulated fashion, often in collections of sub-arrays. Generally, the cells are along columns defined by bit lines which are orthogonal to word lines. See, for example, Eaton, Jr. et al. U.S. Pat. No. 4,389,715 entitled "Redundancy Scheme For A Dynamic RAM" for a general description of a DRAM, and Sud, Hardee, & Heightley U.S. Pat. No. 4,355,377 entitled "Asynchronously Equilibrated and Pre-Charged Static RAM" for a general description of a SRAM.
In such memories, attention is given to the equilibration and precharging circuitry, as in Hardee et al. U.S. Pat. No. 4,494,221 entitled "Bit Line Precharging and Equilibrating Circuit."
Reference is made to FIG. 1 which is a set of representative signals that are common in DRAMS of today's genre. The top waveform illustrates the row address strobe inverse signal called RAS BAR. When RAS BAR is low, the memory is in the active period, but when RAS BAR is high, the memory is in the precharge epoch. The memory alternates between such epochs many times per second. As is well known, DRAMs are volatile and dynamic; that is, typically the data is stored in the form a small amount of charge on a capacitor. This charge leaks away through any of a variety of mechanisms, whereupon the data becomes lost. To prevent this catastrophic result, the memory cell containing the capacitor is repeatedly read and refreshed. When it is read, a sense amplifier operates to determine what datum has been stored in the cell, and rewrites that datum in the cell. Without reading and refreshing, the data will be lost.
The sense amplifier is generally coupled to one or a pair of bit lines which are sometimes referred to as the bit line and bit bar line. In some memories, especially SRAMs, complementary states of the data are stored in the memory cell or in a complementary pair of memory cells. Whether or not such complementary data is stored, the sensing operation, which is used during the refresh operation, involves setting the bit line which is connected to the memory cell to be refreshed to a known value. This value is commonly referred to as the "precharge voltage" or the "equilibrate voltage." The equilibrate voltage causes the bit line to be precharged, and the second waveform in FIG. 1 illustrates the equilibrate voltage or signal which may be called .phi..sub.EQ. It will be seen that .phi..sub.EQ is shifted slightly to the right with respect to RAS BAR; soon after RAS BAR drops low, .phi..sub.EQ drops low. Also, a few nanoseconds after RAS BAR rises to the high state (Vcc), denoting the beginning of the precharge epoch, .phi..sub.EQ likewise rises, typically to the power supply voltage Vcc.
The restoration period normally takes several nanoseconds, and the third waveform in FIG. 1 is .phi..sub.RC. It will be observed that the trailing edge of .phi..sub.RC occurs approximately or nominally 10 nanoseconds after the rising edge of .phi..sub.EQ.
Circuits for precharging and equilibrating the bit lines are well known. FIG. 2 represents a prior art approach in a simplified portion of a DRAM array. One column includes a bit line 10a paired with a bit bar line 11a. Each of them is connected via a respective fuse 12a, 13a to a sense amplifier 14a. Along each bit line may be positioned a plurality of memory cells 15M, and, in a DRAM, a dummy cell 15D for each bit line, coupled to the sense amplifier via fuses 12, 13. Each memory cell 15M illustratively comprises a transistor and a capacitor. One plate of the capacitor is coupled to Vss. The other plate is coupled to the bit line via the transistor, which has a path of controllable conductivity controlled by a voltage on a word line WL. The word lines WL-1 to WL-N make up N rows of the array, and, as seen in FIG. 2, are orthogonal to the column (bit) lines 10, 11. A respective dummy memory cell 15D is included in each column, and is controlled by a dummy word line WL-D. The dummy cell has a capacitance that may be equal to, larger than, or smaller than that capacitance of each memory cells 15M.
An equilibration transistor 16a has a source-drain path which couples bit lines 10a, 11a together whenever the transistor is turned on. The gate electrode of transistor 16a is coupled to receive the equilibration signal .phi..sub.EQ of FIG. 1.
Beside transistor 16a are "keeper transistors" 18a and 20a. Transistor 18a has its source-drain path coupled between a line 22 and bit line 10a. Keeper transistor 20a has its source-drain path coupled between line 22 and bit line 11a. The gate electrodes of transistors 18 and 20 are also coupled to receive the equilibration signal .phi..sub.EQ In this instance where transistor 16, 18 and 20 are n-channel transistors which turn on upon the application of a relatively positive voltage for .phi..sub.EQ, it being understood that other types of switching devices could be used, the transistors upon application of the equilibration signal .phi..sub.EQ equilibrate or equalize the voltages on bit lines 10a and 11a, and couple those bit lines also to receive whatever voltage is applied via line 22.
The column circuitry of FIG. 2 comprising 10a, 11a, 12a, 13a, 14a, 16a, 18a, and 20a can be referred to as columns A and A*. Further columns B and B* with identical construction are located parallel to A and A*. Indeed, a plurality of such like columns collected together in a memory chip form an array or sub-array.
One modification of this prior art approach is shown in Hardee, U.S. Pat. No. 4,791,613 entitled "Bit Line And Column Circuitry Used In A Semiconductor Memory." It uses a different voltage for the equilibration signal applied to the equilibration transistor, and applies the power supply voltage Vcc to the "keeper transistors" 18, 20.
In the prior art, originally bit lines were set to either zero volts or to the power supply voltage Vcc during the precharge or equilibrate operation. Newer DRAMS precharge the bit lines to 1/2 Vcc. To achieve this precharge voltage, the bit and bit bar lines are typically shorted together at the beginning of the precharge cycle. (One bit line has a Vcc level and the other has a Vss level. When shorted, 1/2 Vcc results.) To maintain this voltage, a voltage divider 24 can be formed from a pair of resistors, or transistors being used as resistors, coupled between Vcc and ground as illustrated in FIG. 2. The voltage obtained from the divider is then applied via line 22 to hold the bit lines near to the desired precharge value.
One problem is that today's memories are so large in capacity (have so many memory cells) that a separate power supply voltage could be entertained to maintain the precharge voltage that is applied from line 22 via transistors 18, 20 to the bit lines. However, such an approach is undesirable, as industry does not want to add a separate power supply voltage or an additional pin to carry that precharge voltage.
A problem with precharging the bit lines to some voltage intermediate zero volts and Vcc without a separate power supply for the intermediate voltage is that the precharge voltage has a tendency to leak away during the refresh epoch and cannot be maintained in the event of a shorted bit line. If the precharge voltage does manage to dissipate entirely, the data will essentially be lost because the cell cannot be read by the sense amplifier circuit.
Notice in FIG. 2 that when, during precharge, transistors 16, 18, and 20 are turned on, all of the bit lines are coupled together via line 22. Hence, a large number of bit lines are ganged together during the precharge operation. One problem is that even one bad bit line will ruin the entire memory. If the bit line constantly draws current through a short, the precharge supply from voltage divider 24 will simply be unable to overcome the short, and the entire memory will be inoperative.
To avoid this catastrophic result, fuses 12 and 13 are employed along With testing procedures to identify all such shorted bit lines. The bad bit lines can then be isolated from the circuit by blowing the appropriate fuse 12 (and redundant bit lines can be substituted). This remedy, however, involves the addition of the fuses and the further test procedures which drive up the cost of the memory.
One object of the present invention, accordingly, is to avoid the problem of one bad memory cell or bad bit line spoiling the entire memory.
Another object is to cure the problem of bad bit lines without adding bit line fuses or the like.
A further object of the invention is to eliminate the voltage divider used in the prior art to provide the "hold" or precharge voltage.
Another object of the present invention is to decrease substantially the high standby current exhibited by the prior art.
A worthy object of this invention is to provide a way to hold the bit lines more closely to the desired precharge voltage for an extended duration and with good control over the voltage.
As mentioned supra, the memory cells in the DRAM have a capacitor plate that in the past has been coupled to ground. Current trends are to couple those cell capacitor plates to Vcc/2, which enables the cell capacitor dielectric to be made thin. That is, one-half of the electric field (which normally causes breakdown) can be used. Thus, the prior art may couple the cell capacitor plates to either Vss, Vcc/2, or even Vcc. A typical Vcc/2 circuit is depicted in FIG. 3. FIG. 3 shows a four transistor power supply circuit having a first n-channel transistor 26 having a source-drain path coupled in series with the source-drain path of a first p-channel transistor 28. The drain of transistor 26 is coupled to Vcc, the source of transistor 26 is coupled to an output node 30, node 30 is coupled to the source of transistor 28 and the drain of transistor 28 is coupled to ground. A second n-channel transistor 40 has its source-drain path coupled in series with the source-drain path of a second p-channel transistor 32. Thus, a node 34 is coupled via a resistor 36 to a source of operating voltage, Vcc. Node 34 is coupled to the gate electrode and the drain of n-channel transistor 30. The source of transistor 40 is coupled to the source electrode of p-channel transistor 32. The drain of transistor 32 is coupled to ground (Vss) via a resistor 38 with a node 39 therebetween. It will be understood that the voltage developed at node 34 is 1/2 Vcc+Vtn. The voltage developed at node 39 is 1/2 Vcc-Vtp, where Vtn is an n-channel threshold voltage, and Vtp is a p-channel threshold voltage. The voltage developed at output node 30 is 1/2 Vcc.
The typical 1/2 Vcc circuit, such as that of FIG. 3, draws considerable standby current when coupled to the cell capacitor plates. Ideally, the 1/2 Vcc supply would be provided by a separate low-impedance power supply to prevent plate bounce, but the extra pin for the integrated circuit chip is undesirable. Also, it is nearly impossible to design a low-impedance intermediate value power supply "on chip" while drawing very little current from the main supplies.
Accordingly, a further object of the present invention is to overcome this problem of providing an intermediate voltage to the capacitor plates of the memory cells while controlling the standby current used in that operation.